The invention relates to an integrated semiconductor circuit having at least two transistors, which are both operated with a first operating voltage and which each have a control electrode and a layer of a dielectric adjacent to the respective control electrode. The first and second transistors are connected up in such a way that the first and second transistors are switched with different frequencies on average over time. An average switching frequency of the second transistor is less than an average switching frequency of the first transistor.
Such semiconductor circuits have been customary for decades in semiconductor technology and are predominantly produced from MOSFETs in CMOS technology i.e. as a combination of n-channel transistors and p-channel transistors. It is usual for the source and drain of the transistors to be implanted into the semiconductor substrate after the prior patterning, in their center, of a dielectric, usually made of an oxidic material such as silicon dioxide, with the overlying gate contact.
Depending on the application purpose, vertical transistors with a source-drain channel running perpendicularly to the substrate surface are also produced. Moreover, there are further conceivable configurations of transistors that likewise have a control electrode that, in a similar manner to the gate electrode of a MOSFET, is isolated from the further electrodes of the transistor by a dielectric.
In MOSFETs, the electric field strength penetrating through the dielectric controls the formation of a channel between the remaining transistor electrodes. A switching operation alters the voltage between the gate and the source and, depending on the type of MOSFET, effects or prevents the formation of a channel beneath the dielectric.
In order to enable the channel formation to be controlled as directly and controllably as possible, the dielectric, which is usually a limited aereal region of a layer deposited on the semiconductor substrate is made as thin as possible. The layer thickness of the dielectric, typically being a few nanometers, is significantly less than the layer thickness of the overlying gate layers, but must be large enough to prevent tunneling through the dielectric on account of the fields present. Proceeding from this necessity, the layer thickness of the dielectric is always chosen to be as small as possible, in order to control the transistor optimally.
What are of particular importance for the electrical switching behavior of the transistor are its short-channel behavior and its transistor performance. A decreasing gate length is accompanied by a decrease in the saturation current that can be achieved between source and drain. It is nevertheless necessary, despite the advancing miniaturization of the transistors, to ensure a sufficiently high saturation current. This is all the more important the smaller the dimensioning of the gate length. At the present time, reliable transistors having gate lengths of less than 150 nm are produced.
Also of importance is the threshold voltage, at which the MOSFET switches, i.e. at which the formation or the collapse of the channel between the source and drain commences. The lower the threshold voltage, the more easily the transistor can be controlled.
For these reasons, for decades the layer thickness of the dielectric of the transistors has been made as small as possible and approximated as far as possible to the minimum layer thickness at which, depending on the semiconductor generation, reliable operation of the transistors is still possible.
More complex circuits often have regions in which transistors are supplied with different operating voltages. Roughly, a distinction can be made between low-voltage transistors having an operating voltage of between 1 and 5 V, high-voltage transistors having an operating voltage of between 10 and 20 V and power transistors having an operating voltage of above 40 V. The different supply voltages require the transistors to have dimensions of different magnitudes. However, transistors are dimensioned in different sizes also in the case of significantly smaller voltage differences within a single region, for instance in that of the low-voltage transistors. It is known, for instance, in the case of transistors operated with different supply voltages, to configure the layer thickness of the respective dielectric with different magnitudes in order to achieve a lifetime that is approximately of the same length for both transistors. Thus, differences between the operating voltages of a few volts typically lead to layer thickness differences of the order of magnitude of a few nanometers.
This measure has long resulted in an approximately identical reliability of different transistors in regions of different supply voltages within an integrated semiconductor circuit.
Furthermore, there continue to exist integrated semiconductor circuits whose transistors are configured for a uniform operating voltage.
It is accordingly an object of the invention to provide an integrated semiconductor circuit having transistors that are switched with different frequencies that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the reliability and the controllability of such semiconductor circuits are improved. In particular, the object of the invention is, with the lifetime of an integrated circuit remaining the same, to further improve its controllability at least in partial regions or, with no reduction in the controllability, to affect an overall increase in the lifetime of the circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor circuit. The integrated semiconductor circuit contains two transistors, including a first transistor and a second transistor, operated with an operating voltage. The two transistors are connected up such that the transistors are switched with different frequencies on average over time, the second transistor having an average switching frequency less than an average switching frequency of the first transistor.
The first transistor has a first control electrode and a first dielectric layer disposed adjacent to the first control electrode, and the second transistor has a second control electrode and a second dielectric layer disposed adjacent to the second control electrode. The second dielectric layer has a given thickness that is less than a given thickness of the first dielectric layer.
The object is achieved according to the invention by virtue of the fact that the layer thickness of the dielectric of the second, less frequently switched transistor, i.e. of the second dielectric, is less than the layer thickness of the dielectric of the first, more frequently switched transistor, i.e. of the first dielectric.
The present invention exploits the fact that different transistors of a semiconductor circuit are addressed with different frequencies. The frequency with which a transistor is switched back and forth between its on state and its off state varies depending on the function and configuration of the transistor within the semiconductor circuit.
Semiconductor circuits are usually clocked with a predetermined frequency, so that a check and, if appropriate, a change of the switching states takes place at discrete, very short time intervals. Considered over many clock periods, it is possible to specify a probability value for the probability with which a specific transistor is switched per clock cycle. The switching probability or switching frequency is inversely proportional to the average temporal duration of a switching state of this transistor, i.e. to the average time interval between successive switching times. The latter differs depending on the transistor and may vary by several powers of 10 between transistors of different regions of the semiconductor circuit.
The invention exploits the fact that the probability of tunneling through the dielectric is reduced and hence the lifetime of the transistor is increased if the transistor is switched only very infrequently measured by the clock frequency. In comparison with other transistors, which are switched approximately with the same frequency as the clock frequency, such a transistor has a much longer potential lifetime. Nevertheless, the dimensioning of such transistors in conventional semiconductor circuits does not differ from that of the frequently switched transistors. Only in those semiconductor circuits that have regions with different transistor operating voltages has the layer thickness of the dielectric been varied hitherto over the semiconductor surface.
In contrast, according to the invention, the layer thickness of the dielectric of the transistors that are switched less frequently is reduced further. The dielectric of the transistor is made so thin that its lifetime corresponds approximately to the lifetime of the frequently utilized transistors. In this way, the layer thicknesses of the dielectrics of both transistors are coordinated with one another in a manner dependent on their respective average temporal switching interval. The fact that the layer thickness of the dielectric of the second, less frequently switched transistor (i.e. of the second dielectric) is chosen to be less than the layer thickness of the dielectric of the first, more frequently switched transistor (i.e. of the first dielectric) results in that, with the lifetime of the integrated circuit remaining the same, its controllability is improved in the region of the second transistor.
The layer thickness of the second dielectric is reduced to such an extent that the lifetime of the first and the lifetime of the second transistor are matched to one another. It is not necessary for an infrequently switched transistor to have a lifetime years longer than that of a frequently switched transistor and hence the integrated semiconductor circuit overall. In contrast, the dielectric layer thickness reduction that is performed in a manner dependent on the switching frequency improves the controllability at least of the less frequently switched transistors; their performance and their short-channel behavior are improved. Proceeding from the layer thicknesses that are already kept small, the layer thickness can be reduced still further in those regions in which transistors are addressed infrequently. An even higher degree of controllability is obtained as a result.
The concept of the invention can be applied both to circuits having a uniform supply voltage and to those having different operating voltages. In the latter case, those transistors that have the larger layer thickness can also easily be reduced in size in order to improve the controllability in regions of higher operating voltage. Furthermore, the layer thicknesses of the dielectrics of the smaller transistors can be reduced to an even greater extent if the lifetime of the semiconductor circuit is limited by the region of higher operating voltages.
In all cases, the present invention leads to an improvement of the switching behavior at least in partial regions of the circuit.
With regard to the extent of the layer thickness variation, a preferred embodiment provides for the layer thickness of the second dielectric to be from 1 to 15% less than the layer thickness of the first dielectric. The moderate reduction takes account of the fact that layer thicknesses have already long been optimized to the technically reliable minimum. With regard to this, smaller layer thickness corrections below the range mentioned are still possible, of course, in order to preclude the risk of tunneling through the dielectric.
A preferred embodiment therefore provides for the switching frequency of the second transistor to be a factor of from 100 to 107 less than the switching frequency of the first transistor. Although it is possible to utilize even smaller ratios of the switching frequency with respect to a layer thickness variation, precisely the greatest fluctuations of the switching frequency will give cause for a configuration correction.
Of course, a layer thickness variation is all the more appropriate in the case of still larger differences in the switching frequency.
A preferred embodiment provides for the second transistor to be a selection transistor by which a memory cell in a memory cell array is selected. In a semiconductor memory having a multiplicity of memory cells, an individual cell is naturally addressed very infrequently, namely only when the information of the respective memory cell is interrogated or altered. By virtue of the large number of memory cells in a memory cell array, the selection transistors of memory cells are addressed much more infrequently than other transistors of the same semiconductor circuit. Therefore, large differences in the frequency of the addressing of different transistors occur precisely in semiconductor memories.
A development of the embodiment provides for the first transistor to be a transistor by which a row path, i.e. a word line is selected, to which a multiplicity of second transistors are connected. The addressing of a specific memory cell results from the simultaneous selection of the relevant word line and of the relevant bit line. In this case, quite a lot of memory cells or selection transistors are connected to each word line. If a specific word line is switched or selected, then potentially every memory cell connected to the word line can be interrogated. For this purpose, the corresponding bit line must also be selected. Since quite a lot of selection transistors of individual memory cells are connected to each individual word line, the selection transistors are switched much more infrequently than the transistors that are responsible for the selection of the word line. Thus, in accordance with the development described here, the selection transistors of the memory cells are provided with a thinner dielectric than the selection transistors for the word lines.
A preferred embodiment with regard to the number of second transistors per word line provides for between a thousand and hundred thousand selection transistors to be connected to the row path which includes the first transistor.
A development of the invention provides for a third transistor to be provided, whose operating voltage is less than that of the first and second transistors and which has a third dielectric whose layer thickness is less than the layer thickness of the second dielectric. In this case, the three transistors have three different layer thicknesses of their respective dielectric but are provided with a total of two different operating voltages. Accordingly, the dimensioning of the three transistors is adapted to two supplied thermal powers of different magnitudes per switching operation and to three different switching frequencies that is manifested in a corresponding dimensioning of the transistor dimensions.
A development of this embodiment provides for the third transistor to be a transistor of a data path that forwards information from the memory cells. In semiconductor memories the data pathsxe2x80x94usually running in an interfacexe2x80x94are operated with a lower operating voltage than memory cells, which have to store information for a relatively long time. In this case, the layer thicknesses of the different dielectrics are set among one another in a manner dependent both on the respective operating voltage and on the respective switching frequency.
A further development of the invention provides for at least four transistors each having a dielectric to be provided, the dielectrics having four different layer thicknesses. The embodiment with a total of four different layer thicknesses of the dielectrics can still be produced relatively cost-effectively. In order to alter the layer thickness of the dielectricxe2x80x94generally of the gate oxidexe2x80x94across the semiconductor surface, the substrate surface is configured differently in a manner known per se, for instance provided with different layers or implantations, which results in gate oxide growth rates of different magnitudes. In addition, the gate oxide can also be removed by partial etching-back in a few aereal regions. Each intervention generally requires a mask and hence additional work outlay. However, it leads to two different layer thicknesses of the dielectric. If only two such steps are combined with one another, up to four possible different layer thicknesses and hence a very complex control method for optimization of the switching behavior of the transistors are obtained.
A preferred embodiment provides for the transistors to be MOSFETs and the control electrodes to be gate electrodes. The field-effect transistors can be applied as planar transistors to a gate oxide that has been produced, or also be produced as vertical transistors in specific applications. In addition, any other conceivable construction of a transistor can be optimized with the aid of the present invention. In particular, it is provided that the dielectrics of all the transistors are gate oxides. This applies at least to the dielectric of the first, second and third and also fourth transistor. In terms of fabrication engineering, first a gate oxide whose thickness varies in regions is produced and subsequently patterned in the context of the transistor fabrication.
It is preferably provided that the integrated semiconductor circuit is configured for a defined clock frequency and that the average switching frequency of a transistor is proportional to the duty ratio of the transistor. A characteristic quantity for the switching frequency of a transistor is the duty cycle. The duty cycle designates the average duration of an off or on state of a transistor between successive switching states. The duty cycle thus corresponds to the reciprocal of the switching frequency of the transistor on average over time. The duty cycle is often specified by a natural number. A duty cycle of 1000 results in that a transistor is switched on average after the 1000th clock cycle. On the other hand, the duty cycle is also colloquially expressed as a percentage, which ultimately means the switching frequency. Thus, a xe2x80x9cduty cyclexe2x80x9d of 10% corresponds to a switching probability of 0.1.
Often, transistors predominantly remain in the off state and are only occasionally switched into the on state for a clock period. In the next clock cycle, they are immediately put into the off state again. Since exactly two switching operations are required in each case for such a pulse the switching frequency can readily be specified by the so-called duty ratio. The duty ratio designates the ratio of the time during which a transistor is in its on state in comparison with the time duration during which the transistor is in the off state. The duty ratio, i.e. the ratio of the temporal duration of on state to off state, corresponds to the switching frequency except for a factor of 2.
The invention can be used in any type of semiconductor circuit and, on account of the generality of the concept of the invention, which is not geared toward a specific purpose of the circuit, can be applied to any semiconductor device. In particular semiconductor memories, in particular embedded DRAMs and also logic circuits are appropriate. Memories are distinguished by a high number of memory cells and hence memory transistors whose information is changed extremely infrequently in regions and whose addressing frequency is therefore many orders of magnitude below the clock frequency. Therefore, the inventive variation of the gate oxide thicknesses in memories leads to a particularly large increase in the controllability. This advantage can equally be utilized in embedded DRAMs that are constructed as memory areas in application specific integrated circuits constructed for more complex tasks.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor circuit having transistors that are switched with different frequencies, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.